1. Field of Invention
Embodiments of the present invention relate generally to semiconductor devices having contact barriers and methods of manufacturing the same. More particularly, embodiments of the present invention relate to a semiconductor device including contacts with a large aspect ratio, repeatedly formed to have a fine pitch in a highly integrated semiconductor device, and a method of manufacturing the same.
2. Description of Related Art
As the integration density of semiconductor devices increases, the thickness of interlayer dielectric layers gradually increases and the aspect ratio of contact holes electrically connecting different conductive layers to each other gradually increases. Thus, in a photolithographic process, an aspect ratio of the contact hole, i.e., a ratio of a length of a hole relative to its diameter, is increased while an alignment margin of the contact hole decreases. As a result, it is difficult to form fine contact holes for implementing highly integrated devices using conventional photolithography processes.
For example, when forming a dynamic random access memory (DRAM), a plurality of bit lines are formed to extend along a predetermined direction and then a buried contact is formed to electrically connect a storage electrode of a capacitor located on each of the bit lines to an active region of a semiconductor substrate between the plurality of bit lines. According to such a conventional method, a space between the buried contact and the bit line is very small. For this reason, an electrical short circuit between the buried contact and the bit line may occur. A problem associated with forming buried contacts using a conventional method of manufacturing a semiconductor device will be discussed with reference FIGS. 1 and 2A through 2C.
FIG. 1 is a schematic view of a conventional semiconductor device. FIGS. 2A through 2C are cross-sectional views taken along line II-II′ shown in FIG. 1 and sequentially illustrate a method of manufacturing the conventional semiconductor device of FIG. 1.
Referring to FIGS. 1 and 2A through 2C, reference numeral 10 denotes an active region defined by an isolation region 4 in a semiconductor substrate 2, reference numeral 20 denotes a word line, reference numeral 30 denotes a bit line, reference numeral 12 denotes a first self-aligning contact (hereinafter, referred to as a “first SAC”) formed by the word line 20 through a self-alignment method, reference numeral 14 denotes a second self-aligning contact (hereinafter, referred to as a “second SAC”) formed by the word line 20 through a self-alignment method and reference numeral 40 denotes a buried contact electrically connected to the active region 10 of the semiconductor substrate 2 through the first SAC 12 in a space between two adjacent bit lines 30.
With reference to FIG. 2A, the semiconductor device illustrated in FIG. 1 is manufactured by first forming a first interlayer dielectric layer 28 made of an oxide layer on a plurality of word lines 20 extending along a predetermined direction on the semiconductor substrate 2 (e.g., extending along the y-direction in FIG. 1) and then forming a plurality of bit lines 30 on the first interlayer dielectric layer 28. The bit line 30 extends in a direction perpendicular to the word lines 20 (e.g., extending along the x-direction in FIG. 1). The top surface and sidewalls of the bit lines 30 are respectively covered by a capping layer 32 and an insulating spacer 34, which are formed of a nitride. A second interlayer dielectric layer 36 made of an oxide layer is formed on the plurality of bit lines 30.
As shown in FIG. 2B, a photoresist pattern 38 is then formed on the second interlayer dielectric layer 36 and a contact hole 38a, for forming the buried contact 40, is then formed by anisotropically dry etching the first and second interlayer dielectric layers 28 and 36 using the photoresist pattern 38 as an etching mask. When observed from the top surface of the semiconductor substrate 2, a contact hole formation region “A” opened by the photoresist pattern 38 overlaps with the bit line 30 by a predetermined width W. When anisotropically dry etching the first and second interlayer dielectric layers 28 and 36 using the photoresist pattern 38 as an etching mask, the first and second interlayer dielectric layers 28 and 36 are etched in such a manner that they are self-aligned by the capping layer 32 and the insulating spacer 34 that cover the bit line 30. As a result, the contact hole 38a is formed having a sectional profile shown in FIG. 2B. However, while the first and second interlayer dielectric layers 28 and 36 are etched, a large portion of the capping layer 32 and the insulating spacer 34 around the bit line 30 is consumed, particularly at a corner region of the bit line 30, due to the tolerance limit with respect to dry etching of the capping layer 32 and the insulating spacer 34. As a result, the corner of the bit line 30 may be undesirably exposed because the total depth of the contact hole 38a is typically very deep (i.e., about 4000 Å to 4500 Å). Further, after forming the contact hole 38a, the thickness distribution of the capping layer 32 and the insulating spacer 34 that remain around the bit line 30 becomes poor depending on a position of a wafer due to the limits of etching equipment under such etching conditions.
As shown in FIG. 2C, the buried contact 40 is formed by filling a conductive material in the contact hole 38a. Given the poor state of the thickness distribution of the capping layer 32 and the insulating spacer 34 remaining around the bit line 30, either a short circuit between the bit line 30 and the buried contact 40 occurs at a shoulder portion “S” of the bit line 30 when filling the conductive material in the contact hole 38a or the rate of failures in subsequent processes is increased due to the potential possibility of a short circuit at the shoulder portion “S”. To lower the rate of failures, previous attempts have been made to form an insulating spacer again on the sidewall of the bit line 30 after forming the contact hole 38a. In such a method, however, the bottom area of the buried contact 40 becomes undesirably narrow. As a result, the contact area of the buried contact 40 and the first SAC 12 is reduced, which increases the contact resistance of the buried contact 40 and the first SAC 12.